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Espressif Systems /ESP32 /RMT /CH4STATUS

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Interpret as CH4STATUS

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STATUS0STATE0STATUS

Fields

MEM_WADDR_EX

The current memory read address of channel0.
STATUS

The status for channel0
MEM_RADDR_EX

The current memory write address of channel0.
STATE

The channel0 state machine status register.3’h0 : idle, 3’h1 : send, 3’h2 : read memory, 3’h3 : receive, 3’h4 : wait.
MEM_OWNER_ERR

When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1.
MEM_FULL

The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range.
MEM_EMPTY

The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range.
APB_MEM_WR_ERR

The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range.
APB_MEM_RD_ERR

The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data